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Name of the Candidate:[Private]
Name of the Post Applied:Embedded System Engineer
Job related skills / software: VHDL, Verilog, Microprocessor and Microcontroller, Digital Design Concepts, VHDL RTL Coding, Transistor Circuit Theory and CMOS
Category:Design Engineering
Sub Category:Embedded System Design Engineer
Years of Experience:0 years
State:Andhra Pradesh
Salary Expected per Month(Rs):25,000 to 30000
Highest Qualification attained:M.Tech
Major / Specialization:Electronics and Communication
Email Id:[Private]
Are you looking for job now?:Yes
Can the recruiter contact you?:Yes
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Resume Format / CV Sample Template / Example / Model :


Saurabh Plot No.15, Gummadi Raj Reddy Colony, Risala Bazaar,
P.O Bolarum, Secunderabad-10 (A.P)
E-Mail  : dsaurabh.kumar AT gmail.com
Contact No. 09030870340

To achieve a prominent position where I can use my skills effectively and improve further that helps my career and which leads to the growth of the organization by riding on my strength.

M.Tech (ECE) Digital Systems and Computer Electronics Sreenidhi Institute of Science and Technology, JNTU-Hyderabad 2011-2013 77.15
B.Tech Electronics and Communication Jyothishmathi college of Engineering and Technology, JNTU-Hyderabad 2007-2011 73.40
XIIth (AISSCE) Non-Medical (PCM) Air Force School, Ambala Cantt, CBSE 2005-2006 61.40
Xth (AISSE) General K.V.No.1, Ambala Cantt, CBSE 2003-2004 62.60

 Good understanding of fundamentals of Transistor circuit theory and CMOS.
 Good knowledge of Verilog and VHDL RTL coding.
 Good knowledge of Digital Design Concepts.
 Implemented a VLSI project during my Graduation.
 Good knowledge of Linux, C and C++ programming.
 Good Knowledge of Microprocessor and Microcontroller.
Operating Systems  : C, C++, Linux.
Packages  : MS Office and MS Power Point etc.

 Attended work shop on “PTSP”.
 Attended work shop on “Nano-Technology” and “Nano-Electronics”.
 Participated in National Workshop on RTOS and its Applications in Embedded Systems.

 Participated in the JNTU-H Zone ‘C’ Inter Collegiate Cricket Tournament-2010.
 Participated in the state level Engineering Collegiate Cricket Tournament at Nexus State Challengers Cricket Tourney 2008-09.
 Won the Cricket Tournament in JCET.
 Participated in PROMETHEAN in BVRIT College.

 Good team person and enjoy working in a team.
 Always owed with “can-do spirit”.
 Ability to adapt to changing situations.
 Willing to work hard with Sincerity andHonesty.
Qualified PGECET Entrance Exam for M.Tech conducted by “Osmania University, Hyderabad” with 2730 Ranking.

Project Title  : Detection of Errors on Serial Communication Lines in RTOS-Based Systems.
(Embedded and VLSI domain)
Team Size  : Individual
Hardware  : Spartan 3e FPGA Kit
Software’s  : GNU MIPS Tool Chain, VMware Player, Xilinx ISE, iMPACT.
Description  : This project is based on Embedded and VLSI domain.

The main focus will be on the detection of the errors on the serial communication lines. This is achieved by using a hardware approach with the combination of Cyclic Redundancy Check and Real Time Operating System (RTOS). During execution of these programs, the proposed system exposed to Electromagnetic Interference (EMI) according to the international standard for voltage transients, voltage dips and short interruptions on the serial communication lines of electronic systems.
Published Paper in M.Tech in Reputed Journals “International Journal of Engineering Research and Application” (IJERA) and International Journal of Engineering Trends and Technology (IJETT).

B.TECH  :(Final Year)
Project Title  : A spurious power suppression technique for multimedia/DSP Applications
(VLSI Domain)
Institute Name  : Krest Technologies
Team Size  : 2-Members
Software  : Modelsim
Description  : This project is based on the VLSI domain. The main aim of the project i.e. A Spurious-Power Suppression Technique (SPST) is to reduce the power dissipation of combinational VLSI designs for multimedia/DSP purposes. The proposed SPST separates the target designs into two parts, i.e., the most significant part (MSP and LSP), and turns off the MSP when it does not affect the computational results to save power.

Project Title  : An intelligent ambulance with control to traffic light (Embedded Domain)
Institute Name  : Vector
Team Size  : 3-Members
Software  : Keil u Vision
Description  : In this project we are overriding existing traffic signal by using intelligent traffic controller. In the present scenario most of our precious time is wasted due to fixed time limit. Due to the wastage of time we lose precious life because delay in reaching the hospital on time. This can be overcome by using intelligent traffic controller.

Name  : Saurabh Kumar
Father’s Name  : Sushil Kumar
Nationality  : Indian
Date of Birth  : 12 December 1988
Permanent Address  : H.No:390, Near Veterinary Hospital, Vill. & P.O Raipur Rani, Teh & Distt. Panchkula, Haryana PIN-134204
Hobbies  :Cricket, Basketball, Volleyball, Listening to music, Watching Television, Reading books.
Language Known  : English, Hindi.


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