Biodata |
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| Name of the Candidate | : | [Private] |
| Name of the Post Applied | : | VLSI Designer |
| Job related skills / software | : | Wide knowledge of VLSI design technology including design tools and environments in advanced sub-micron process technologies, Proven experience in RTL coding of DSP communication algorithms, Knowledge and experience in mixed signal design and/or high speed logic design is an advantage |
| Category | : | Design Engineering |
| Sub Category | : | Electronics Design/ VLSI Engineer |
| Years of Experience | : | 0 years |
| State | : | Andhra Pradesh |
| Gender | : | Male |
| Salary Expected per Month(Rs) | : | 25,000 to 30000 |
| Highest Qualification attained | : | B.Tech. : Bachelor of Technology |
| Major / Specialization | : | Electrical and Electronics |
| Email Id | : | [Private] |
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| Are you looking for job now? | : | Yes |
| Can the recruiter contact you? | : | Yes |
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KADIYALA PRUDHVI
Kakinada, Andhra Pradesh
Email : prudhvikadiyala6 AT gmail.com
OBJECTIVE :
Seeking a challenging atmosphere that encourages learning, creativity and provides exposure to the emerging latest technologies and scope for professional growth. Also,where I can utilize my energy, skill, creativity and experience to the fullest in order to achieve the corporate goals and establish a long-term relationship with the company.
EDUCATION :
** Completed B.Tech in Electrical and Electronics Engineering (EEE) from Aditya College of Engineering, Surampalem with 60 % in 2019.
** Completed Diploma in Electrical and Electronics Engineering (EEE) from L.K.B. Polytechnic College,Ravulapalem with 69% in 2015.
** Completed SSC from Santhiniketan Public school,with 65% in March, 2011
TECHNICAL SKILLS :
** Wide knowledge of VLSI design technology including design tools and environments in advanced sub-micron process technologies
** Proven experience in RTL coding of DSP communication algorithms
** Proven experience in the areas of synthesis and timing
** Proven experience with the following tools : MATLAB, Cadence design tools, Verilog
** Knowledge and experience in mixed signal design and/or high speed logic design is an advantage
** Knowledge on Basics of JAVAlanguage.
** Good understanding of knowledge on software testing life cycle and test methodologies like agile methodology.
** Knowledge on defect tracking tools likejir
STRENGTH :
** Mathematical ability
** Self -motivation
** Creative and innovative
** Quick learning and problem solving.
** Enthusiastic to learn about new things.
** Excellent Communication skills.
** Decision making skills.
** Organizational skills.
** Leadership skills.
PERSONAL DETAILS :
Full Name : Kadiyala Prudhvi
Fathers Name : Kadiyala Satyanarayana
Date of Birth : 26th Nov 1994
MaritalStatus : Unmarried
DECLARATION :
All the information furnished above is true and correct to the best of my knowledge and belief.
Providedanopportunityto serve your organization, would begratefulandperformtothebest to prove my candidature.
PLACE :
DATE :
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