Biodata |
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| Name of the Candidate | : | Neelam Swathi |
| Name of the Post Applied | : | VLSI Designer |
| Job related skills / software | : | C, VHDL, verilog HDL, CADENCE, Low-Power Pulse-Triggered Flip-Flop Design Based On a Signal Feed through Scheme |
| Category | : | Design Engineering |
| Sub Category | : | Electronics Design/ VLSI Engineer |
| Years of Experience | : | 0 years |
| State | : | Telangana |
| Gender | : | Female |
| Salary Expected per Month(Rs) | : | 25,000 to 30000 |
| Highest Qualification attained | : | M.Tech. : Master of Technology |
| Major / Specialization | : | VLSI & Embedded Systems |
| Email Id | : | nlm.swathi7211 AT gmail.com |
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| Are you looking for job now? | : | Yes |
| Can the recruiter contact you? | : | Yes |
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Neelam Swathi:
nlm.swathi79 AT gmail.com
M.Tech (VLSI& Embedded Systems)
Mobile [:+91 9177456187
Career Objective :
To work in an organization that provides ‘Competitive Environment’ with “Challenging Assignments” that enables me to apply and upgrade my Wisdom. Also aim at steady professional growth and self development.
Educational Profile :
** M.Tech(2012-Dec 2014) in VLSI & Embedded Systems from Kakatiya University (KITS, WGL) with 81.00%.
** B.Techin Electronics and communications engineering from JNTU (BITS, NARSAMPET) in the year of 2012 with 80.19%.
** Intermediatein MPC from Kakatiya Mahila Junior College, Hanamkonda in the year of 2008 with 90.4%.
** S.S.Cfrom Fatima Girl’s HIGH School, Kazipet in the year of 2006 with 86.33%.
Technical Skills :
** Programming languages : C, VHDL, verilog HDL, CADENCE.
** Operating Systems : WINDOWS 07/XP.
** Packages : MS office.
Strengths :
** Comprehensive problem solving ability.
** Positive attitude.
** Enthusiastic in team work.
Academic Main Project in M.Tech :
TITLE : Low-Power Pulse-Triggered Flip-Flop Design Based On a Signal Feed through Scheme
Implementing a IEEE paper “Low-Power Pulse-Triggered Flip-Flop Design Based On a Signal Feed through Scheme” in which A low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase Clock latch based on a signal feed-through scheme is presented.
The proposed Design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better Speed and power performance.
OTHER ACTIVITIES :
** Participated in paper presentation on “Accumulator based 3 weight pattern generation”.
** Participated in paper presentation in Shrestah’10 conducted by 5th National Level Technical Student’s Symposium.
** Participated in paper presentation in “PARIKARAN” and got merit certificate.
** Certified in DB2 exam conducted by IBM.
PROFILE :
** Full Name : Neelam Swathi
** Date of Birth : 2/7/1991
** Marital Status : Spinster
** Languages known : English and Telugu
DECLARATION:
I hereby declare that all the above information furnished is true to the best of my knowledge and belief.
Place : Warangal.
Date : (N.SWATHI)
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