RACHANA.K.BEmail id :rachana990 AT yahoo.inCareer Objective :
To work in a challenging environment, which upgrades my knowledge, improves my skill and provides a room to give out my best to the organization.Academic Qualification :
M.Tech-VLSI(Design) from SRINIVAS INSTITUTE OF TECHNOLOGY with
B.Tech-ECE from KVG COLLEGE OF ENGINEERING with
PU from VIVEKANANDA PU COLLEGE,PUTTUR with 76%
SSLC from KVG ENGLISH MEDIUM HIGH SCHOOL,SULLIA with 85%Technical Skills :Operating system : WINDOWSProgramming languages : C, JAVA.HDLs :VerilogFPGA Tools : Xilinx ISESoftware :modelsimProject :Ti Sponsored links :
tle : REALISATION OF ENCODING ARCHITECTURE FOR THE REDUCTION OF ENERGY CONSUMPTION USING VERILOG HDLDescription : As technology shrinks the power consumption is also increased.Achievements :
Attended two days workshop on LATEX SOFTWAREPersonality Traits :
Good verbal and communication skills.Personal Details :Name : RACHANA K BFather name : K S BHASKARDate of Birth : 01/10/1990Nationality : IndianHobbies : Listening Music.Languages Known : English, Kannada,Hindi & KannadaDeclaration :
I hereby declare that all the statements made in the form of correct to the best of my knowledge and belief.Date :Place :
(RACHANA K B)
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