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Name of the Candidate:[Private]
Name of the Post Applied:ECE Electronics Communication Engineer / Lecturer
Job related skills / software:Modelsim, Xilinx, Matlab, C
Category:Teaching Lecturer Faculty
Sub Category:Lecturer
Years of Experience:0 years
State:Karnataka
Gender:Female
Salary Expected per Month(Rs):Negotiable
Highest Qualification attained:M.Tech. : Master of Technology
Major / Specialization:VLSI Desgin and Embedded Systems
Email Id:[Private]
 
Are you looking for job now?:Yes
Can the recruiter contact you?:Yes
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OBJECTIVE             

To utilize my Technical knowledge in growth of the organization and gain practical work experience & expand my knowledge base. I work to the fullest of my capabilities with result oriented approach and remain open for new challenges in the best of my organization’s interest.

WORK EXPEXIENCE

Worked as project trainee with Tata Elxsi Ltd., Bangalore (Duration: 14 months). The scope of the project is to design LTE downlink transmitter chain for implementation on  FPGA.

Ø  Gone though LTE specification document to get to know the requirements.

Ø  Writing code in Verilog HDL using Xilinx tool and simulated using Modelsim tool.

Ø  Design of Scrambler.

Ø  Design of Modulation mapper.

Ø  Design of OFDM signal generator block.

Ø  Verification of FFT module.

 

TECHNICAL SKILLS

Languages              :      C, Verilog HDL, VHDL, Microprocessor/Microcontroller, Matlab.

Tools                      :      Xilinx, Modelsim, Matlab.

Operating Systems :     Windows XP/7.

 

ACADEMIC PROFILE

Examination

Discipline/Specialization

School/ College

Year of Passing

Percentage

 

M.Tech

 

VLSI Design and Embedded Systems

Nagarjuna   College of Engineering and Technology

 

   2012

 

74.04

 

B.E

 

Electronics and Communication

MalnadCollegeof Engineering

 

2009

 

 

66.47

 

Diploma

 

Electronics and Communication

Govt. Residential Women’s Polytechnique, Shimoga

 

2006

 

74.5

 

S S L C

-

Jagadeeshwara

English Medium High

School, Kalasa

 

2003

 

75.52

 

 

ACADEMIC PROJECT DETAILS

  

Project Name     :  Design and implementation of digital transceiver based on LTE specification

Description       : The project was aimed at designing on the transmitter architecture of the LTE downlink data channel PDSCH comprising Scrambling, Modulation and receiver architecture comprising Demodulation and Descrambling as described in the LTE specifications, so that it can be implemented on FPGA. It also aimed at OFDM signal generation. Coding is done using Verilog HDL.

 

Project Name     :Verification of SPICE level model

Description       : This is done using MATLAB. Programs are written in MATLAB to obtain curves for linear, saturation and subthreshold conduction. These are then joined together but results in discontinuity in the characteristics. This is solved by using mathematical smoothing functions between different operating regions.

Project Name       : Implementation of SR-Flipflop by using CMOS

Description        : Implementation is done on Cadence Virtuoso and analysis is done. Design is made by 180 nm technology. The NAND gate is formed at transistor level and its operation is tested. Then SR-flipflop is formed using this NAND gate.

 

Project Name       : Image Compression Using Code Composer Studio

Description      : The objective of the project is to develop a compression algorithm which satisfies JPEG standard in-order to reduce the storage and transmission costs while maintaining good quality.

 

Project Name       : Electronic Eye With Security Dial Up

Description        : This project is based on sensor activation. When we are far away from the house, if anyone tries to enter the house by any means, the device generates musical tone continuously for more than 40seconds. The device also dials out previously stored telephone number and   gives the musical tone, so that we can understand that something wrong at house.

 

EXTRA CURRICULAR ACTIVITIES

 

Ø  3 days workshop on “Analog Design using cadence Tool.”

Ø  Presented paper, “Design of Downlink Architecture for LTE using FPGA ”, at National Conference on Signal Processing and Communication held at R.V.
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College of Engineering, Bangalore 2012.

Ø  Participated in “Do-it yourself” state level technical projects exhibition 2005-06.

Ø  Participated in Carom event and stood second place at college level.

Ø  Participated in Cricket and secured first place at college level.

Ø  Participated in school level quiz and throw ball competition and received applauds.

Ø  Participated in NSS camps.

Ø  Obtained certificate on successful completion of “Aware for office management ” course.

 

PERSONAL DETAILS

 

     Name                                           :       Usha. K.S

     Father’s Name                             :       Shankaranarayana. K

     Date of Birth                               :       27-02-1988

     Gender                                        :       Female

     Languages Known                      :       English, Kannada and Hindi.

     Permanent Address                     :      D/o Shankarnarayana. K, Opp. Syndicate Bank,

                                                                 Main Road, Kalasa- 577124

     Nationality                                  :       Indian.

     Passport Details                           :      G3468780 / Validity till: June 5th 2017

     Hobbies                                       :       Watching Movies, Listening Music, Playing games.

             

DECLARATION

     I here by declare that all the above-furnished information is true to best of my knowledge and belief.

Date    :                                                                                                         Yours sincerely,

 

Place    :                                                                                                           

                                                                                                                        (Usha K S)                                                                                                   
                                                                                                                  

 

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