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Digital Circuit Design Verification Engineer Resume Sample, Experience : 2 years

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Name of the Candidate:[Private]
Name of the Post Applied:Digital Circuit Design Verification Engineer
Job related skills / software:System Verilog, Source Insight, Matlab, Cadence Tools
Category:Design Engineering
Sub Category:Electronics Design Engineer / Designer
Years of Experience:2 years
Salary Expected per Month(Rs):Negotiable
Highest Qualification attained:B.Tech. : Bachelor of Technology
Major / Specialization:Electronics and Communications
Email Id:[Private]
Are you looking for job now?:No
Can the recruiter contact you?:No
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Resume Format / CV Sample Template / Example / Model :


Eager to contribute highly applicable engineering application skills and ability to personalize service delivery to analyzing engineering needs and translating them into executable strategies for the firm.

IT professional with comprehensive technical skill set and expertise in automation process improvement, systems integration, requirements analysis, workflow design, leadership, quality assurance, software development.
Proficient problemsolver who envisions technical perspectives to develop workable solutions.
Motivated achiever who guides organizations in applying technology to business settings, provides added value, and creates project deliverables in a timely manner.

A +1.5 year of experience in corporate field.
Worked 6 months as a project trainee and designated as design and verification engineer at Insilica semiconductor including experience in VLSI front end design and verification.
Had a formal cooperate under training for 6 months in embedded system including expertise in C, C++, UNIX, Operating System, Real Time OS and Microcontroller.
Currently working as a software engineer associate for Kyocera wireless India ltd with a 1 year experience in the domain of telecom including expertise in messaging field (SMS, EMS and MMS).

Languages C, C++, Verilog, System verilog.
OS UNIX, Real time OS, Window.
Concepts Networking, Microcontroller, BREW.
Software Visual basic, Source insight, Matlab, Cadence Tools, Modelsim, BREW Platform.

Project in C : Implementation of dictionary using Hashing and Linked list.
Platform used : UNIX
Language : C
Duration : 1 month

Project in C++ : Data base management and calculator.
Platform used : UNIX
Language : C++
Duration : 1 month

Project in VLSI front End : SMIA: (Standard Mobile Imaging Architecture) The SMIA Functional Specification objective is to fully standardize the electrical, control and image data interfaces for raw Bayer sensor modules targeted at mobile applications.
The main objective is driven by the requirement to be able to connect ANY SMIA compliant sensor to ANY SMIA compliant host system with matching capabilities and get a working system with acceptable performance.
Platform used : UNIX
Tools : Cadence tools, Modelsim, ICCR.
Language : Verilog, System Verilog, Assertion based verification, TCL.
Duration : 6 months

Project in Mobile Application : Worked on mobile UI software.
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Handled and supported messaging related issues such as SMS, EMS and MMS for different targets (mobile) for Kyocera Wireless India Ltd. This includes knowledge of C language, BREW API’s and platform, REX OS, debugging techniques by using JTAG setup and other tools and software’s such as CRMDB, Coverty, QXDM and RACAL setup.
Platform used : BREW Platform.
Tools : CRMDB, Coverty, and QXDM and RACAL setup.
Languages and concept : C, SMS protocols and BREW API’S.
Duration : January 2008 to February 2009.

Highly interested to apply my self with the basic knowledge in the field of VLSI, Microcontroller and Processor, Digital Image Processing, Digital Electronics, Communication System, Wireless communication and Analog Electronics.

Course Academic Year Institute Name of Board / University % or CGPA Division
B.Tech ECE 2003 07 ICFAI Institute of Science&Technology, Bangalore. ICFAI University 8.78 1st
XII 200102 Shri Guru Govind Singh College,Patna BIEC(State Board), Patna 67% 1st
X 2000 D.B.R.K. Jallan High School,Patna B.S.E.B(State Board), Patna 68% 1st

Scholarship holder throughout engineering.
Won awards in sports events (cricket, table tennis, football etc).
Technical Event organizer in College Fest.



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