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Fresher Associate System Engineer Resume Sample

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Name of the Candidate:[Private]
Name of the Post Applied:Associate System Engineer
Job related skills / software:Knowledge of Networking and C, Verilog, Automatic toll collection & number plate recognition using image processing on FPGA
Category:IT / Computer
Sub Category:System Administrator / Engineer
Years of Experience:0 years
Salary Expected per Month(Rs):Negotiable
Highest Qualification attained:B.E. / BE : Bachelor of Engineering
Major / Specialization:Telecommunication
Email Id:[Private]
Are you looking for job now?:Yes
Can the recruiter contact you?:Yes
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Resume Format / CV Sample Template / Example / Model :


Email  : rakesh290491 AT gmail.com
Cell No  : +91 9035718806

I am a fresher in the corporate culture, but ready to take on the world and accept challenges. Utilizing my communication skills, smart working ability, fresh thoughts and assertive behavior, to benefit the organization and contribute substantially to its development, is the prime concern of my career.

B.E (Telecommunication) Atria Institute Of Technology, Anandnagar, Bangalore-24. 2013 70.17%
P.U.C (PCME) K.L.E’s independent PU college Bangalore-560010. 2009 72.16%
S.S.L.C The Bangalore Education Society, Bangalore-560003. 2007 85.44%

Computer languages  : C.
Hardware language  : Verilog.
Software  : Matlab2012Ra, Xilinx, Microsoft office.

Title  : Automatic toll collection & number plate recognition using image processing on FPGA.
Implemented at Atria Institute of Technology under the guidance of Sudhir Rao (Research associate at Indian Institute of Science) of Worldserve Education.
Description  : This project was implemented for highways toll collection application which would be able to collect toll fee of the vehicle without stopping it. We developed algorithms to detect the vehicle and capture the image as it approaches the toll gate.
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Using image processing, the input image feeds are used for number identification and extraction. The software model was developed in Matlab, and coding was done in Verilog which was then downloaded onto the FPGA (Spartan3).
Tools Used  : Matlab, Xilinx, Simulink.

Actively participated in various inter school sports activities.
Participated in sub-junior, junior levels in All India General Knowledge.
Participated in district level long jump, 100m running race.

Ability to work with a team, involving, planning and coordinating.
Ability to rapidly build up relationships and set up trust.
Hardworking and honest.
Good Communication skills.

Name  : Rakesh V
Father’s Name  : Late. Venkatesh T
Nationality  : Indian
Date of birth  : 29th April 1991
Sex  : Male
Marital status  : Single
Languages Known  : English, Hindi and Kannada.
Hobbies  : Listening to music, Surfing internet on latest technology, Playing cricket, watching movies.
Address  : #1516,13th cross, Mariyappanapalya, Bangalore 560021.

I hereby declare that the above information is true to the best of my knowledge and belief.

Place  : Bangalore
(Rakesh V)


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