Design Engineering >> Electronics Design/ VLSI Engineer 
Fresher Physical Design Engineer Resume Sample

DILEEP KUMAR .T
Email Id : dileep.t1995 AT gmail.com

CAREER OBJECTIVE :
To be associated with an organization that provides career development opportunities and an environment to enable me to contribute in its growth with hard work and dedication.

EDUCATIONAL QUALIFICATION :
** Master of Technology VLSI design and embedded systems Autonomous under VTU Dr. Ambedkar Institute of Technology/2019 8.6 (CGPA)
** Bachelor of Engineering Electronics and communication VTU Don Bosco Institute of Technology. Bangalore /2017 64%
** Pre-University College PCMB Department of Pre-University Education East West pre university College Bangalore/2013 65.83%
** Higher Secondary School State syllabus Karnataka Secondary Education Examination Board Annie beasant convent and high schoo Bangalore/2011 73.76%

TOOLS AND LANGUAGES :
EDA Tools  : Cadence Innovus, Cadence Genus, Cadence-Virtuoso, Xilinx ISE design suit (V 14.7)
Programming language  : C
Scripting language  : TCL (Basic knowledge)
HDL  : Verilog

TECHNICAL SKILLS :
** Familiar with ASIC flow (RTL to GDSII)
** Hands on experience in Floor Planning, Power Planning, Placement, CTS, Routing, STA and sign off analysis.
** Have knowledge on Digital electronics, and CMOS design, & IC fabrication.
** Having theoretical knowledge on Physical Verification (PV).

TRAINING PROGRAM :
** One year VLSI Physical design using cadence tool training at Dr. AIT R&D and VLSI centre.
** Power electronics and its applications at Apex high tech institute (central government) Bangalore.

SEMINAR :
** Participated in seminar on ‘Input and output connectivity for Digital system’ held at Dr. AIT Bangalore-560056
** Participated in Seminar on ‘ Carry Look Ahead Adder using Brent Kung Adder’ held at DR. AIT Bangalore-560056.

ACADEMIC PROJECTS :
Project title : “ASIC implementation and performance analysis of 128 bit DADDA multiplier”
Description : This project gives the design of 128 bit Dadda multiplier by using compression technique. The power consumption and area of this Dadda multiplier reduces by the use of compression technique. The physical design of 128 bit Dadda multiplier is carried out by using Cadence tool with 45nm technology and 9 metal layers.

Project title : “Design of low power and low delay multiplexer using CMOS combinational logic by using Cadence virtuoso tool”
Description : This project gives the design of low power and low delay multiplexer by using the combinational logic.


This proposed design of multiplexer gives lesser delay and less power consumption by using a combinational logic. Cadence virtuoso tool is used to design the proposed multiplexer.

Project title : “Design of low delay Brent Kung adder”
Description : This project gives the design Low delay Brent kung adder which is type of parallel adder. In many adders the delay is produced mainly because of carry propagation from one stage to the next stage but in this proposed Brent kung adder a new technique for carry propagation has been designed which reduces the delay in the system. The designed by writing a verilog code and this verilog code is simulated using Xilinx ISE 14.7 tool.

Project title : “Smart home energy management system using renewable energies”
Description : In this project the smart home energy management is performed using renewable energies like solar energy and wind energy. The main objective of this project is to save the energy that regularly used by home appliances. The energy obtained from the solar and wind is stored and it is utilized for the operation of home appliances.

Project title : “Home automation using ESP8266”
Description : This project gives Home automation using ESP8266 it also called as nodemcu and also android application has been developed for home automation. The main objective of this project is to control the home appliances by using a android application. The complete design is performed by using a tool called aurdino IDE.

WORKSHOPS ATTENDED :
Title  : “VLSI TESTING AND VERIFICATION”.
Date  : 11-Apr-2018 to 13-Apr-2018.
Organized by  : Department of ECE, Dr. AIT Bangalore
Description  : This workshop event started with the basics of RTL design carried on to hands on session using EDA tool for functional verification of the design using system verilog, verilog and effective usage questasim for simulation and concluded with the automation of VLSI design using python programming language and by using EDA tools.

Title  : “ARM CORTEX M3”.
Date  : 26-Dec-2017 to 28-Dec-2018
Organized by  : Department of ECE and TCE, GSSS Institute of Technology in Association with Electro Systems Associates Bangalore
Description  : This Workshop Event Started With Basics Of Importance of ARM Processors, Carried Onto the Hands On Sessions On ARM Development Board Using ARM Cortex M3.

DATE :
PLACE :