CURRICULUM VITAE :
SRI GIRISH NITTALAEmail : srigirishn AT gmail.comPhone : +91- 9944576599Career Objective :Objective :
To obtain a position that will enable me to use my strong technical skills, educational background, and ability to work well with the reputed organization.Academic Qualification :
M.Tech- VLSI Design (1st Year) 2016 (pursuing) VIT Universisty VIT University 7.88
B.Tech (ECE) 2009-2013 Kakinada Institute of Engineering And Technology-2 JNTU KAKINADA 72.36%
INTERMEDIATE (M.P.C) 2007-2009 Narayana Junior College, Kakinada. Board Of Intermedidate Education 93%
S.S.C 2007 Bhashyam Public School, Kakinada. Board Of Secondary Education 86.6 %Curriculum Seminar & Project :CMOS VGA IMPLEMENTATION IN S BAND FOR LINEARIZATION AND NOISE MINIMIZATION :Subject : SET Project - II (M.Tech-2nd Semester)
The gain of the differential pair is controlled by the variable voltage. The gain of the amplifier is of non - linearized and prone to the noise. So, we have to reduce the nonlinearity and noise of the VGA. A low power and linearized VGA is proposed and analysis is done.
Team Size-3LOW LATENCY PARALLEL MULTIPLIER :Subject : ASIC LAB Project (M.Tech-2nd Semester)
8-bit high performance multiplier which gives high speed for evaluating result and which is an advanced version of baugh wooley multiplier the main motive of this paper is reduce the propagation delay and thus how achieve high performance with gpdk 90nm process technology.
Team Size-3REDUCING POWER IN SRAM BASED PROCESS UNITS VIA DYNAMIC APPROACH :Subject : SET Project – I (M.tech-1st semester)
The work presents methodology to reduce the dynamic power dissipation in processor by minimizing verification and re-designing of the hardware. The implemented work requires less amount of hardware and circuit modification. The circuit is oriented to the implementation in TSMC-90 nm CMOS standard cell technology.
Team Size-3Design Of AMBA APB :
The AMBA APB should be used to interface to any peripherals which are low bandwidth and do not require the high performance of a pipelined bus interface.Teamsize : 1ELECTRONIC TOLL COLLECTION SYSTEM USING RFID & GSM :Subject : Main Project (B.Tech)
The project describes that this system is fully automated and reduces the human error which brings a great evolution in the method of toll system by its flexibility.This active RFID technology will increase efficiency. Sponsored links :
With the elimination of human interaction in the entire toll collection process, it is possible to create an efficient toll collection process.
Team Size-5Technical Skills :
Cadence virtuoso,NC launch, RC compiler,SoC Encounter,LEF.
ALTERA quartus-II, modelsim
Scripting languages Basics of PERL,TCL
Programming languages Verilog HDL
Basics of CAchievements :
Secured 1st position in 1st year during under graduation.
Elected as effective Leader for the year 2012 in our college.
Merit certificate from IIIT HYDERABAD in ROBOTICS workshop.
Winners of team activity program conducted at our college “KIET”.Active participations :
Participated in contraptions event in SHAASTRA 2010, a national level tech fest at IIT MADRAS.
Participated in national level leadership summit conducted by project management institute (PMI) at Hyderabad.Personal profile :Name : N. SRI GIRISHDate of Birth : 04-06-1992Father’s name : N.V.S. Bhaskara Rama SarmaLanguages Known : English, Telugu, German (Beginner)Nationality : IndianTemporary Address : D.No: 7-9-25/4, Sambamurthy Street, Ramarao pet,
Kakinada ,E. G. Dist, Andhra Pradesh-533004DECLARATION :
I hereby declare that the above written particulars are true to the best of my knowledge and belief.Place : VELLOREDate : 26-07-2015
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